Semiconductor wafer processing requires more strict control of wafer temperature to reduce wafer temperature excursion during processing, as device geometries shrink to ever smaller dimensions. For example, high temperatures can adversely affect the sharp semiconductor junction profiles required for small feature sizes. Limiting workpiece (or semiconductor wafer) temperature during processing is also necessary whenever processing is carried out using photoresist masking of device features, in order to avoid heat-induced degradation of the photoresist.
In plasma processing of wafers, the wafer temperature can exceed many hundreds of degrees C., particularly where large RF bias power levels are employed at low chamber pressure, where heat transfer by gas convection and conduction is poor (and radiation heat transfer is also poor). For example, in plasma immersion ion implantation reactors, RF bias power applied to the wafer may be many kWatts, particularly where deep implant depths are required. The wafer must be actively cooled to limit temperature rise to maintain photoresist integrity or avoid material degradation. Typically electrostatic chucks are used to clamp the wafer to a cooled or temperature controlled surface. In a conventional Unipolar or Monopolar electrostatic chuck, a voltage is applied across a dielectric layer between wafer and electrode. The “dielectric” layer may be a near ideal insulator or may be a semiconductor. The “dielectric” layer may be a deposited film or a bulk solid material, such as ceramic or semiconducting material. The electrostatic field across the structure formed by the wafer, dielectric layer, air or vacuum gap and the electrode produces an attractive force between the wafer and the dielectric layer. Alternatively, conventional Bipolar electrostatic chucks have more than one electrode. A voltage is applied across two or more electrodes separated from the wafer by the dielectric layer. The electrostatic fields across the structure formed by the wafer, dielectric layer, air or vacuum gap and each electrode produces an attractive force between wafer and dielectric layer.
Typical electrostatic chucks employ a heat transfer gas between the wafer and the electrostatic chuck surface to promote heat transfer. Helium is a preferred gas due to its high thermal conductivity, but other gases are sometimes used. For high RF power levels (high heat load on the wafer), the helium pressure must be correspondingly high to provide a sufficient heat transfer rate. Unfortunately, such high gas pressure reduces the threshold RF power level (or RF voltage level) at which arcing, gas breakdown, or dielectric breakdown occurs within the helium gas passages in the chuck, in the interface between electrostatic chuck and wafer, or in the wafer support pedestal. Such problems have become more critical as greater demands are placed on processes such as plasma immersion ion implantation processes. For example, certain implantation processes may require implant doses in excess of 1017 cm−3, requiring the exposure of the wafer to high RF power levels for several minutes, during which the wafer temperature can reach over 400° C. without active cooling or over 200° C. with conventional electrostatic chucks. Similar problems can occur in other applications, such as plasma or reactive ion etching etching, plasma chemical vapor deposition, physical vapor deposition, etc.
Another problem is that the top surface of the electrostatic chuck must have many open channels (channels machined into the chuck top surface) through which the helium cooling gas is pumped to provide thermal conductance between the wafer and the chuck. Such channels have many sharp edges, which create contamination of particles on the wafer backside or contamination of the process. These edges may have radii on the order of microns, so as to be very sharp. Contamination is caused by scratching the wafer backside over the sharp edges of the channels and/or by the deleterious effects of high electric fields in the vicinity of each sharp edge, which can lead to arcing about the sharp edges, removing material from the chuck surface into the plasma. A goal of wafer processing in fabricating extremely small features on the wafer is to limit the number of contaminant particles on each wafer backside to not more than tens of thousands or less. The contaminants either contaminate the current wafer or are passed along to contaminate other processes or reactors that handle the same lot of wafers.
The use of high pressure gas to cool the wafer makes the electrostatic chuck so vulnerable to arcing, gas breakdown or dielectric breakdown, that the applied RF bias voltage cannot exceed several kV in typical cases. Moreover, the ability of a conventional electrostatic chuck to cool the wafer is inadequate for many of the future processes being contemplated, its heat transfer coefficient for the wafer being less than about 1000 Watts/m2° K. What is needed is an electrostatic chuck (wafer support pedestal) which can withstand about 10 kV of RF bias voltage without arcing, gas breakdown, or dielectric breakdown, which has a heat transfer coefficient of at least 1000 Watts/m2° K (between wafer and electrostatic chuck) and has a heat transfer coefficient of at least 5000 Watts/m2° K (between electrostatic chuck dielectric surface and heat sink or cooling circuit), minimizes scratching and particle formation at wafer backside, does not contaminate the wafer backside, and has material properties compatible with the plasma processing environment (consumption rate, non-source of contaminants).